The present invention relates to a semiconductor device. More particularly, the invention relates to a semiconductor device including a DP-SRAM (dual port static random access memory) cell or a 2P-SRAM (two port static random access memory) cell.
There is the widespread use of SOC (system on chip) or ASIC (application specific integrated circuit) for high-speed communication and image processing and DP-SRAM or 2P-SRAM having two input/output ports on microcomputers.
Generally, the DP-SRAM or the 2P-SRAM has two input/output ports. Each port independently has a clock terminal or a timing generation circuit. FIG. 1 is a block diagram illustrating a configuration of a 2P-SRAM 101 having port A used as a write port and port B used as a read port. The 2P-SRAM 101 includes a memory cell array 102 provided with memory cells 103 in rows and columns, an I/O circuit 104, a port-A peripheral circuit 120A, and a port-B peripheral circuit 120B. The memory cell 103 is configured as a DP-SRAM cell. The memory cell array 102 is provided with a port-A word line WLA, a port-B word line WLB, a pair of port-A bit lines BLA and /BLA, and a pair of port-B bit lines BLB and /BLB. These lines are coupled to the memory cells 103.
The I/O circuit 104 includes an input latch 105, a write driver 106, multiplexers 107 and 108, a sense amplifier 109, and an output latch 110.
The port-A peripheral circuit 120A includes a timing generation circuit 111A, an address pre-decoder 112A, write latch circuits 113A and 114A, and a write word line driver 115A. Similarly, the port-B peripheral circuit 120B includes a timing generation circuit 111B, an address pre-decoder 112B, latch circuits 113B and 114B, and a word line driver 115B.
The 2P-SRAM 101 in FIG. 1 uses port A as a write port and port B as a read port. Port A includes an input latch 105, a write driver 106, a multiplexer 107, and a port-A peripheral circuit 120A. Port B includes a multiplexer 108, a sense amplifier 109, an output latch 110, and a port-B peripheral circuit 120B. Ports A and B are supplied with different clock signals. Ports A and B operate asynchronously. Specifically, the timing generation circuit 111A for port A is supplied with clock signals CL_A. The timing generation circuit 111B for port A is supplied with clock signals CL_B. The circuits for port A operate in synchronization with clock signal CL_A. The circuits for port B operate in synchronization with clock signal CL_B.
The DP-SRAM is discussed in Y Ishii, et al., “A 28 nm dual-port SRAM macro with screening circuitry against write□read disturb failure issues”, A-SSCC 2010 literature number Industry1-2, for example.
FIG. 2A is a block diagram illustrating a configuration of a system using the 2P-SRAM 101 illustrated in FIG. 1. Two CPUs 130A and 130B are coupled to the 2P-SRAM 101. The two CPUs 130A and 130B are supplied with different clock signals to operate. Specifically, the CPU 130A operates in synchronization with clock signal CL_A (supplied to port A for the 2P-SRAM 101). The CPU 130B operates in synchronization with clock signal CL_B (supplied to port B for the 2P-SRAM 101). The CPU 130A supplies port A for the 2P-SRAM 101 with address ADD_A and chip selection signal CE_A. The CPU 130B supplies port B for the 2P-SRAM 101 with address ADD_B and chip selection signal CE_B.
An application may supply a common clock signal to ports A and B. FIG. 2B illustrates a configuration of a system used for such a case. The system illustrated in FIG. 2B supplies common clock signal CL to the CPUs 130A and 130B, and ports A and B of the 2P-SRAM 101 in common. The entire system operates in synchronization with common clock signal CL.
Japanese Unexamined Patent Publication No. 2010-135025 discloses the technology that allows one-port SRAM to operate as multi-port SRAM based on an STS (super time sharing) system. The multi-port SRAM disclosed in this publication allows a read port and a write port to operate in synchronization with one clock signal.    Patent Document 1: Japanese Unexamined Patent Publication No. 2010-135025    Non-Patent Document 1: Y Ishii, et al., “A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues”, A-SSCC 2010 literature number Industry1-2.